Integrated circuits are critical to the success of many technology areas, and especially critical to the continued growth of the telecommunications industry. Semiconductor devices in the form of integrated circuits are the cornerstone of many telecommunications systems involving a broad spectrum of different circuits, many of which require high frequency capabilities. High frequency telecommunications circuits typically require the use of inductors to either tune a circuit to a particular desired frequency, to perform critical circuit functions such as maintaining a critical current flow, or to filter and eliminate undesired electrical noise from desired signals.
If a collection of inductors is needed to allow a particular integrated circuit device to perform correctly, the use of discrete inductors that are separate from the integrated circuit device may give rise to implementation problems due to the need for many interconnections. This situation has driven the industry to move in the direction of integrating as many of these needed inductors as possible into the semiconductor device itself. However, the integration of an inductor into a semiconductor device creates other problems due to the inductor""s magnetic nature.
The magnetic field associated with a conductive coil forming an inductor is a well known donut or torus shaped structure, usually having an elliptical cross-section. This magnetic field alternates with the frequency applied to the inductor and may cause interfering effects within the semiconductor device itself. The generation of spurious currents due to this magnetic field may produce several undesirable effects. One of these is to reduce the effectiveness of the conductive coil""s ability to perform as an inductor due to energy losses.
It is well known that the Q of an inductive circuit is a figure of merit that relates the energy stored to the energy dissipated or lost. High Q inductor circuits (a Q of 10 or greater) conserve sufficient energy to allow an appropriate inductive response. Alternately, low Q inductor circuits (a Q of three or less) lose a sufficient portion of the energy applied, often through the generation of eddy currents in the semiconductor device, causing them to perform poorly as inductive elements. Eddy currents are minimized in a semiconductor layer that corresponds to lower dopant concentrations thereby providing a layer having comparatively higher resistivity.
An example of an integrated circuit, that will not support a high Q inductor, has a highly conductive substrate and a highly resistive epitaxial (EPI) layer grown on the substrate. This integrated circuit is typical of a fundamental building block used in many current communications microchips. This substrate may have a positive dopant, such as boron, with a P+ dopant concentration that is typically greater than 1018cmxe2x88x923making the substrate highly conductive electrically. The EPI layer also has a positive dopant but with a reduced or P- dopant concentration of about 1015cmxe2x88x923 making the EPI layer highly resistive.
The highly conductive substrate is used to prevent a functionally destructive phenomenon known as latch-up. Latch-up occurs when a voltage is applied to a semiconductor device in a direction opposite to the normal operating polarity. Latch-up is reduced in a semiconductor layer corresponding to higher dopant concentrations, which thereby provide a layer having comparatively higher conductivity (lower resistivity). A highly resistive substrate, however, would exacerbate the latch-up phenomenon.
High frequency communications microchips require that inductors be integrated into a microchip to achieve a required circuit performance and size, as stated earlier. If an integrated inductor were formed over the EPI layer under discussion, the inductor would induce eddy currents into the highly conductive substrate thereby incurring a large energy loss. To be energy efficient and therefore low loss, the integrated inductor would have to be formed over a highly resistive substrate. A semiconductor device, therefore, must incorporate trade-offs within its design to eliminate the generation of spurious currents and successfully accommodate integrated inductors. However, achievement of the required trade-offs currently requires many additional process steps in the construction of the semiconductor device thereby adding substantial manufacturing time and therefore cost to the semiconductor wafer.
Accordingly, what is needed in the art is a simplified and more cost-effective way to accommodate integrated inductors into semiconductor wafers.
To address the above-discussed deficiencies of the prior art, the present invention provides for a method of manufacturing a simplified high Q inductor substrate and a semiconductor device having that substrate. In one embodiment, the method for manufacturing the simplified high Q inductor substrate comprises forming a base substrate over a semiconductor wafer, wherein the base substrate has a given dopant concentration and then forming an epitaxial (EPI) layer over the base substrate that uniquely has differently doped regions. The EPI layer includes epitaxially forming a first doped region in the EPI layer over the base substrate and then epitaxially forming a second doped region in the EPI layer over the first doped region. The first doped region preferably has a dopant concentration greater than the given dopant concentration of the base substrate, and the second doped region has a dopant concentration less than the first doped region.
The present invention therefore introduces the broad concept of manufacturing a simplified high Q inductor substrate through the forming of the EPI layer containing at least two dopant concentrations. These differently doped regions provide a balance in the semiconductor device between maximizing the Q for an integrated inductor formed in the device and maintaining a required latch-up resistance for the device.
Forming the base substrate, in one embodiment of the present invention, includes doping the base substrate with a p-type dopant to a dopant concentration ranging from about 1014 cmxe2x88x923 to about 1016cmxe2x88x923 wherein a dopant concentration of about 1015cmxe2x88x923 is typical.
In an embodiment to be illustrated and described, epitaxially forming an EPI layer includes epitaxially forming an EPI layer having first and second doped regions to a thickness ranging from about 3 xcexcm to about 7 xcexcm.
Epitaxially forming a first doped region in the EPI layer, in an alternate embodiment, includes doping the first doped region with a p-type dopant to a dopant concentration equal to or greater than about 1017cm3. In a further aspect of this embodiment, a dopant concentration of about 1018cmxe2x88x923 is used, and the first doped region has a thickness ranging from about 0.5 xcexcm to about 2 xcexcm.
In yet another embodiment of the present invention, epitaxially forming a second doped region over the first doped region includes doping the second doped region with a p-type dopant to a dopant concentration ranging from about 1014cmxe2x88x923 to about 1016cmxe2x88x923 wherein a dopant concentration of about 1015cmxe2x88x923 is typical. The second doped region has a thickness ranging from about 3 xcexcm to about 5 xcexcm.
In another aspect, the present invention provides a semiconductor wafer that comprises a base substrate that is formed over a semiconductor wafer and that has a given dopant concentration. An epitaxial (EPI) layer is formed over the base substrate, which includes at least first and second doped regions. The first doped region is located over the base substrate and has a dopant concentration greater than the given dopant concentration of the base substrate. The second doped region is located over the first doped region and has a dopant concentration less than the first doped region. While two doped regions have been specifically set forth, those who are skilled in the art will appreciate that other embodiments of the present invention could provide for more than two differently doped regions within the EPI layer.
The foregoing has outlined, rather broadly, preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.